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Re: [PATCH linux-next v3 6/7] ASoC: rsnd: add avb clocks

Hi Morimoto-san

Thanks for your comments

On 2018/12/05 17:58, Kuninori Morimoto wrote:
Hi Jiada

There are AVB Counter Clocks in ADG, each clock has 12bits integral
and 8 bits fractional dividers which operates with S0D1ϕ clock.

This patch registers 8 AVB Counter Clocks when clock-cells of
rcar_sound node is 2,

Signed-off-by: Jiada Wang <jiada_wang@xxxxxxxxxx>

+static void clk_avb_div_write(struct rsnd_adg *adg, u32 data, unsigned int idx)
+static u32 clk_avb_div_read(struct rsnd_adg *adg, unsigned int idx)
As I mentioned before, I think we can avoid confusable parameter by

	static void clk_avb_div_write(struct clk_avb *avb, u32 data)
	static u32 clk_avb_div_read(struct clk_avb)	

	div = clk_avb_div_read(avb);
	clk_avb_div_write(avb, val | div);
right, I forgot to update this, will address it in next version
+static struct clk *clk_register_avb(struct device *dev, struct rsnd_adg *adg,
+				    unsigned int id, spinlock_t *lock)
+	struct clk_init_data init;
+	struct clk_avb *avb;
+	struct clk *clk;
+	char name[8];
+	const char *parent_name;
+	if (IS_ERR(adg->clkadg))
+		return ERR_PTR(-ENODEV);
I think adg->clkadg will never hit to IS_ERR().
It will have NULL or correct pointer.
right, will update this in next version
	clk = devm_clk_get(dev, "adg");
	if (!IS_ERR(clk))
		adg->clkadg = clk;

And this "adg" clock is strange.
see below

+	avb = devm_kzalloc(dev, sizeof(*avb), GFP_KERNEL);
+	if (!avb)
+		return ERR_PTR(-ENOMEM);
+	parent_name = __clk_get_name(adg->clkadg);
This parent_name is very strange to me.
AVB parent clk is "AUDIO_CLK_A/B/C/I" (= clk_a/b/c/i in this driver)
or "AUDIO_CLK_OUT_A/B/C/D" (= audio_clkout/1/2/3 in this driver).
And we don't have "adg" clock.
Please double check it.
I have some local device-tree change, which expends 'adg' register range and add "adg" clock to rcar_sound node which refer to newly added 'adg' clock (S0D1ϕ) in this patch-set

the change looks like the following

                        compatible =  "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";
                        reg =   <0 0xec500000 0 0x1000>, /* SCU */
-                               <0 0xec5a0000 0 0x100>,  /* ADG */
+                               <0 0xec5a0000 0 0x140>,  /* ADG */
                                <0 0xec540000 0 0x1000>, /* SSIU */
                                <0 0xec541000 0 0x280>,  /* SSI */
                                <0 0xec740000 0 0x200>;  /* Audio DMAC peri peri*/
                        reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

-                       clocks = <&cpg CPG_MOD 1005>,
+                       clocks = <&cpg CPG_MOD 922>, <&cpg CPG_MOD 1005>,
                                 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
                                 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
                                 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
@@ -1856,7 +1856,7 @@
                                 <&audio_clk_a>, <&audio_clk_b>,
                                 <&cpg CPG_CORE R8A7795_CLK_S0D4>;
-                       clock-names = "ssi-all",
+                       clock-names = "adg", "ssi-all",
                                      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
                                      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
                                      "ssi.1", "ssi.0",


Best regards
Kuninori Morimoto