Re: [PATCH 3/3] eeprom: at25: Split writes in two SPI transfers to optimize DMA
- Date: Wed, 10 Oct 2018 21:47:44 +0000
- From: Trent Piepho <tpiepho@xxxxxxxxxx>
- Subject: Re: [PATCH 3/3] eeprom: at25: Split writes in two SPI transfers to optimize DMA
On Wed, 2018-10-10 at 15:40 +0200, Geert Uytterhoeven wrote:
> Currently EEPROM writes are implemented using a single SPI transfer,
> which contains all of command, address, and payload data bytes.
> As some SPI controllers impose limitations on transfers with respect to
> the use of DMA, they may have to fall back to PIO. E.g. DMA may require
> the transfer length to be a multiple of 4 bytes.
> Optimize writes for DMA by splitting writes in two SPI transfers:
> - The first transfer contains command and address bytes,
> - The second transfer contains the actual payload data, now stored at
> the start of the (kmalloc() aligned) buffer, to improve payload
Does this always optimize? A master capable of an of aligned 18 byte
DMA xfer would now have a 2 byte xfer that would probably be PIO
followed by a 16 byte DMA.
Or writing 14 bytes to the EEPROM has changed from an aligned 16 byte
write to a 2 byte and a 14 byte, which is now worse for the 4 byte
multiple requirement master which can use any DMA anymore.
It seems like an enhancement to the DMA code to look more like a
efficient memcpy() that aligns the address, then xfers efficient
blocks, then finishes the sub-block tail would be more generally
Or more simply, given an aligned 18 byte xfer, the driver should do an
aligned 16 byte DMA and then two more bytes.