[DMA-engine Question] inconsistent policy of src_addr_widths, dst_addr_widths
- Date: Wed, 10 Oct 2018 21:00:01 +0900
- From: Masahiro Yamada <yamada.masahiro@xxxxxxxxxxxxx>
- Subject: [DMA-engine Question] inconsistent policy of src_addr_widths, dst_addr_widths
When I wrote my DMA engine driver,
I had difficulty in understanding
what to set to the struct dma_device members.
For example, src_addr_widths.
I see two driver groups regarding this.
[A] BIT(DMA_SLAVE_BUSWIDTH_*_BYTES) are OR'ed
For example, st_fdma.c
[B] DMA_SLAVE_BUSWIDTH_*_BYTES are directly OR'ed without BIT()
For example, sh/rcar-dmac.c
Which is correct?
If we go with [A],
BIT(DMA_SLAVE_BUSWIDTH_64_BYTES) i.e. BIT(64)
would not fit in ddevice->src_addr_widths whose type is u32.
If we go with [B], the following formula is met.
DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES
We never know whether 3_BYTES is supported,
or it is just a combination of 1_BYTE and 2_BYTES.