Re: [RFC PATCH 00/16] x86/split_lock: Enable #AC exception for split locked accesses
- Date: Tue, 29 May 2018 10:25:13 -0700
- From: Fenghua Yu <fenghua.yu@xxxxxxxxx>
- Subject: Re: [RFC PATCH 00/16] x86/split_lock: Enable #AC exception for split locked accesses
On Tue, May 29, 2018 at 09:39:01AM -0700, Dave Hansen wrote:
> On 05/27/2018 08:45 AM, Fenghua Yu wrote:
> > ==Detect Split Lock==
> > To detect split lock, a new control bit (bit 29) in per-core TEST_CTL
> > MSR 0x33 will be introduced in future x86 processors. When the bit 29
> > is set, the processor causes #AC exception for split locked accesses at
> > all CPL.
> > The bit 29 specification in MSR TEST_CTL is published in the latest
> > Intel Architecture Instruction Set Extensions and Future Features
> > Programming Reference.
> The fact that this is per-core is pretty important, right? Where does
> that get mentioned?
The fact that TEST_CTL is per-core is NOT mentioned in the Instruction
Set Extensions or SDM.
(By the way, ISE and SDM don't mention other important details, e.g.
the fact that operand is fetched to cache before split lock is checked.
Without the fact, it's hard to explain that only split lock generates bus
lock in chapter 8.1.4 in SDM vol3.)
I was told that TEST_CTL is per-core by the split lock hardware designer.
And I do find that the MSR is per-core on the currently only processor
that has split lock implementation.
As you can see handling per-core TEST_CTL needs consideration of locking
But the code is supposed to work even if TEST_CTL is per-thread (or even
per-socket) in future.
Maybe I can add "Current TEST_CTL implementation is per-core. The patches
are supposed to work even when TEST_CTL is per-thread (or even per-
socket) in future as well."?