Re: [PATCH v2] pinctrl: tegra20: Provide CDEV1/2 clock muxes
- Date: Wed, 16 May 2018 17:05:30 +0300
- From: Dmitry Osipenko <digetx@xxxxxxxxx>
- Subject: Re: [PATCH v2] pinctrl: tegra20: Provide CDEV1/2 clock muxes
On 16.05.2018 15:23, Linus Walleij wrote:
> On Fri, May 4, 2018 at 12:55 AM, Dmitry Osipenko <digetx@xxxxxxxxx> wrote:
>> Muxing of pins MCLK1/2 determine the muxing of the corresponding clocks.
>> Make pinctrl driver to provide clock muxes for the CDEV1/2 pingroups, so
>> that main clk-controller driver could get an actual parent clock for the
>> CDEV1/2 clocks.
>> Signed-off-by: Dmitry Osipenko <digetx@xxxxxxxxx>
>> Reviewed-by: Marcel Ziswiler <marcel@xxxxxxxxxxxx>
>> Tested-by: Marcel Ziswiler <marcel@xxxxxxxxxxxx>
>> Tested-by: Marc Dietrich <marvin24@xxxxxx>
>> Acked-by: Peter De Schrijver <pdeschrijver@xxxxxxxxxx>
>> v2: This patch is factored out from the v1 clk/DT series so that it could be
>> applied separately.
> Patch applied unless Stephen W protests.
> Please include swarren on future patches to this driver.
I think previously get_maintainer script suggested driver authors, probably it
changed sometime ago. I'm pretty sure that Stephen follows the linux-tegra ML
(Stephen, are you?) and would have jumped into the thread if there was anything
wrong in the patch, though indeed won't hurt to ping him for this patch explicitly.
Stephen, please let me know if you disagree with anything in this patch.