Re: [PATCH RFC 2/2] KVM: x86/vPMU: ignore access to LBR-related MSRs
- Date: Wed, 6 Dec 2017 20:02:07 +0300
- From: Jan Dakinevich <jan.dakinevich@xxxxxxxxxxxxx>
- Subject: Re: [PATCH RFC 2/2] KVM: x86/vPMU: ignore access to LBR-related MSRs
On Wed, 6 Dec 2017 07:57:28 -0800
Andi Kleen <ak@xxxxxxxxxxxxxxx> wrote:
> If you do all this it's only a small step to fully enable LBRs for
It is quite simple in a case where guest LBR-related MSRs matches host
ones. They could be handled by MSR load/store areas, I suppose.
In other cases, it could be expected the different amount of these MSRs
and different theirs base values (e.g. Nehalem vs Core). Guest MSRs
could be both subset and superset of host MSRs, so additional efforts
to support this would be required.
> Just need to allow them to be written, expose PERF_CAPABILITIES too,
> and start/stop them on entry/exit, and enable context switching
> through perf in the host.
> That would be far better than creating a frankenstate where LBR is
> there but mostly broken on some KVM versions.