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Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode




Hi, Andrew,

It will cause data corruption, at least on MIPS:
step 1, dma_map_single
step 2, cache_invalidate (no writeback)
step 3, dma_from_device
step 4, dma_unmap_single
If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) may cause data lost.
 
Huacai
 
------------------ Original ------------------
From:  "Andrew Morton"<akpm@xxxxxxxxxxxxxxxxxxxx>;
Date:  Thu, Sep 14, 2017 05:52 AM
To:  "Huacai Chen"<chenhc@xxxxxxxxxx>; 
Cc:  "Fuxin Zhang"<zhangfx@xxxxxxxxxx>; "linux-mm"<linux-mm@xxxxxxxxx>; "linux-kernel"<linux-kernel@xxxxxxxxxxxxxxx>; "stable"<stable@xxxxxxxxxxxxxxx>; 
Subject:  Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode

 
On Wed, 13 Sep 2017 17:20:51 +0800 Huacai Chen <chenhc@xxxxxxxxxx> wrote:

> In non-coherent DMA mode, kernel uses cache flushing operations to
> maintain I/O coherency, so the dmapool objects should be aligned to
> ARCH_DMA_MINALIGN.

What are the user-visible effects of this bug?