[PATCH 1/2] drm/vc4: Fix DSI T_INIT timing.
- Date: Fri, 17 Mar 2017 16:41:30 -0700
- From: Eric Anholt <eric@xxxxxxxxxx>
- Subject: [PATCH 1/2] drm/vc4: Fix DSI T_INIT timing.
The DPHY spec requires a much larger T_INIT than I was specifying
before. In the absence of clear specs from the slave of what their
timing is, just use the value that the firmware was using.
Signed-off-by: Eric Anholt <eric@xxxxxxxxxx>
drivers/gpu/drm/vc4/vc4_dsi.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index 160f981d1cf4..3bad8bad32a2 100644
@@ -1094,7 +1094,17 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
- DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000),
+ /* T_INIT is how long STOP is driven after power-up to
+ * indicate to the slave (also coming out of power-up) that
+ * master init is complete, and should be greater than the
+ * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The
+ * D-PHY spec gives a minimum 100us for T_INIT,MASTER and
+ * T_INIT,SLAVE, while allowing protocols on top of it to give
+ * greater minimums. The vc4 firmware uses an extremely
+ * conservative 5ms, and we maintain that here.
+ DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns,
+ 5 * 1000 * 1000, 0),