Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver
- Date: Fri, 17 Mar 2017 10:30:33 -0400
- From: Agustin Vega-Frias <agustinv@xxxxxxxxxxxxxx>
- Subject: Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver
On 2017-03-17 10:24, Agustin Vega-Frias wrote:
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own
Access to each individual PMU is provided even though all CPUs share
the slices. User space needs to aggregate to individual counts to
a global picture.
The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
perf stat -a -e l3cache_0_0/read-miss/
perf stat -a -e l3cache_0_0/event=0x21/
Signed-off-by: Agustin Vega-Frias <agustinv@xxxxxxxxxxxxxx>
Documentation/perf/qcom_l3_pmu.txt | 25 ++
drivers/perf/Kconfig | 10 +
drivers/perf/Makefile | 1 +
drivers/perf/qcom_l3_pmu.c | 825
include/linux/cpuhotplug.h | 1 +
5 files changed, 862 insertions(+)
create mode 100644 Documentation/perf/qcom_l3_pmu.txt
create mode 100644 drivers/perf/qcom_l3_pmu.c
This was built and tested on top of v4.11-rc2.
The perf fuzzer was run overnight and no stability issues were found.
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a
Linux Foundation Collaborative Project.